Acronym	Backronym	Definition	Operation
tPL	Parity Latency	DDR4 Only. External command parity error check.	Delays all commands from the memory controller until it ensures that there are no parity errors, through an even parity bit check.
tRCD	Row/RAS to Column/CAS Delay	Activate command to an internal read/write command delay.	Allows time for the needed page (row) to be found, activated (opened), and then have its data (word line) -- this is true for the entire column width (or depth of columns) in that row -- be read into the sense amplifiers (one for each memory cell) via the bit lines (column data transfer channels between the sense amps and memory cells). This is known as a "destructive read" process, as it depletes the charge in both the memory cells and the bit lines, rendering them unusable for other pages (rows) in that bank (3D grid of memory rows and columns).
tAL	Additive Latency	External read/write command delay.	Delays read/write commands from the memory controller until tRCD has eleapsed.
tCL\|AA	Column Address/Access Strobe/Select Latency \| Address Access	The internal read command to first bit of data output latency.	The time it takes to find the needed column starting address that data is output from.
tRL	Read Latency	Total read command Latency.	Equal to the tAL + tCL (+ tPL for DDR4).
tCWL/WCL	Column Address/Access Strobe/Select Write Latency	The internal write command to first bit of data input latency.	The time it takes to find the needed column starting address that data is input to.
tWL	Write Latency	Total write latency.	Equal to tAL + tCWL (+ tPL for DDR4).
tBL/C	Burst Length/Chopped	The maximum (tBL), block of column locations that are selected/bits of data that are transmitted for read or write commands, and half that amount (tBC).	For DDR1 to 4, 8 bits over 4 clock cycles (tBL), or 4 bits/2 clocks (tBC) of data are input or output, to or fro memory, from a block of 8 or 4 column locations, respectively. For DDR5 it's 16(optional 32 for x4 devices) bits/8(16) clocks (tBL), or 8 bits/4 clocks (tBC).
tWR	Write Recovery	Write operation recovery time.	Addendum to a final write operation (tCWL + tBL/tBC) before a precharge (close) operation is executed, as a grace period to make sure that the data has properly been written to the sense amplifiers.
tRTP	Read To Precharge	Internal read command to precharge command delay.	The minimum amount of time that has to elapse between an internal read command and a precharge (close) command, and doesn't have to wait for a read operation (tCL + tBL/tBC) to complete.
tWTP	Write To Precharge	Internal write command to precharge command delay.	The minimum amount of time that has to elapse between a final internal write command and a precharge (close) command, but does have to wait for a final (see tWR) write operation to complete. Equal to tCWL + tBL + tWR.
tRP	Row/RAS Precharge	Precharge operation period.	The period where data from the sense amplifiers is written into the activated (opened) page (row), the bit lines (column data transfer channels between the sense amps and memory cells) are precharged/recharged (depending on whether that bank [3D grid of memory rows and columns] is accessed again), and the page is closed. Sort of a reverse of tRCD.
tRAS	Row Address/Access Strobe/Select	Activate command to a precharge command period.	The period from when an activate command is sent to activate (open) a page (row), to when a precharge (close) command is sent.
tRC	Row/RAS Cycle	Activate command to an activate or refresh command period.	Period in which tRAS and tRP happen, therefore equal to tRAS + tRP.
tREFI(1/2/4/sb)	REFresh Interval(Whole/Half/Quarter/same bank)	The average input or output of data to all banks (3D grid of memory rows and columns) in a rank (group of memory chips) (ab), or the same bank (sb), period. Can be divided (tREFI2/4/sb).	Per specification, a period of 7.8 us (8192 refreshes every 64 ms) for DDR1 to 4, and 3.9 us (8192/32) for DDR5, that can be divided (tREFI2/4/sb) if the memory controller deems it best, or based on the memory's temperature (higher temperature = lower period), where data can go in and out of memory before a refresh (tRFC) must happen to all banks in a rank (ab), or just a specific bank in every bank group (sb). Refresh intervals can be delayed 9 (8 for DDR1, and 5 for DDR5), 17 (N.A. to DDR1, and 9 for DDR5), 33 (N.A. to DDR1 and DDR5), or the number of banks per bank group + 1 (DDR5 only) times, depending on the tREFI being either 1, 2, 4, or sb, respectively.
tRFC(1/2/4/sb)	ReFresh Cycle(Whole/Division)	The activating (opening) and precharging (closing) of pages (rows) that were not accessed during the corresponding tREFI, in all banks (3D grid of memory rows and columns) in a rank (group of memory chips) (ab), or a specific bank in every bank group (sb), period. Can be divided (tRFC2/4/sb).	After tREFI, essentially tRCD and tRP happen back-to-back for a time, to pages (rows) that were not accessed during the just exited tREFI period, leaving them (the memory cells) refreshed/recharged. Its divisions (tRFC2/4/sb) correspond to their respective tREFI counterpart (tREFI2/4/sb), except not to the same division amount (not a half, quarter, etc). Refrese cycles can be dealyed 8 (7 for DDR1, and 4 for DDR5), 16 (N.A. to DDR1, and 8 for DDR5), 32 (N.A. to DDR1 and DDR5), or the number of banks per bank group (DDR5 only) times, depending on the tREFI being either 1, 2, 4, or sb, respectively.
tSTAG	STAGger	Refresh operation staggering between ranks (group of memory chips).	In order to limit the maximum current to specification, refreshes are staggered so that only one rank is refreshed at a time.
tCCD	CAS to CAS Delay	CAS command to CAS command delay.	Delays read or write commands between banks (3D grid of memory rows and columns).
tRRD	Row/RAS to Row/RAS Delay	Activate command to activate command delay.	Delays activate commands between banks (3D grid of memory rows and columns). It's also the time it takes to complete a page (row) activation.
tFAW	Four Activations Window	Four banks (3D grid of memory rows and columns) consecutive activation window.	The time window in which four back-to-back bank activations can occur, to limit the current. The minimum time being 4 * tRRD/_S, per specification.
tWTR	Write To Read	The start of a write transaction To an internal read command delay.	During this time, data written to the input buffers is moved into the sense amplifiers.
tRTW/RDWR	ReaD To WRite	Internal read command to internal write command Delay.	The delay between an internal read command and an internal write command.
tRDRD	ReaD to ReaD Delay	Internal read command to internal read command Delay.	The delay between internal read commands.
tWRWR	WRite to WRite Delay	Internal write command to write command Delay.	The delay between internal write commands.
tWRRD	WRite to ReaD Delay	Internal write command to read command Delay.	The delay between an internal write command and an internal read command.
tMRD	Mode Register set Delay	MRS command delay/cycle time.	The time it takes to complete a write operation to a mode register, and the minimum time that must elapse between MRS, or valid for DDR5, commands (see Commands for definition).
tMOD	Mode register set to On-die termination update Delay	MRS (Mode Register Set) command (see Commands for definition) to ODT resistances update, or non-MRS command, delay/cycle time.	The time that must elapse between a MRS and non-MRS command, except for DES (DESelect) and NOP (No OPeration) commands (see Commands for definition), to allow for the MR's settings to update.
tCKE	ClocK Enable	Clock enable minimum pulse width.	The amount of time it takes to exit power down mode.
tXS	eXit Self refresh mode	Self refresh mode exit to command delay.	The delay between exiting self refresh mode and issuing a command.
tXP	eXit Power down mode	Power down mode exit to command delay.	The delay between exiting power down mode and issuing a command.